By default this test profile is set to run at least 3 times but may increase if the standard deviation exceeds pre-defined defaults or other calculations deem additional runs necessary for greater statistical accuracy of the result. The use of VFP vector mode is deprecated in AR Mv7. It looked like this may be possible in the FreeRTOS int handler, as interrupts are enabled just before the OEI register is written, but swapping the int enable and int clear didn’t solve the problem. The Cortex-A9 FPU provides an optimized solu tion in performance, power, and area for embedded applications and high performance for general-purpose applications. The external L2 cache in theory would allow customers to design a smaller version of Cortex-A9 that didn’t incorporate an L2, and the design allowed configurations that didn’t include the coherency logic. I believe this could potentially cause a 1023, if interrupts are re-enabled in the handler before the interrupt source has been cleared, and the PMR hasn’t been updated with the value of the current int priority, so the same interrupt would be triggered again (interrupting itself, thus the 1023). The Cortex-A9 made use of a hardware block to manage cache coherency among one to four cores in a CPU cluster, with an external L2 cache. I noticed that the FreeRTOS Cortex A9 int handler doesn’t write the Priority Mask Register (PMR), and so doesn’t support nested interrupts. This led me to suspect a timing issue in the FreeRTOS Cortex A9 interrupt handler (maybe writing the IAR and re-enabling interrupts before the write had time to clear the int) but I can’t find anything suspect in there. Using WriteThrough, NoWriteAllocate (slower) and the problem goes away. The problem only occurs when the MMU is flagging the DDR3 RAM area (from which the code is running) as WriteBack, WriteAllocate (the ‘fastest’ setting). Sometimes I get the expected interrupts (timer, ethernet packet rx etc) followed immediately by an int 1023, sometimes I only get an int 1023 (and don’t receive the interrupt I was expecting). Cache coherence has three different levels: Each writing operation seems to. The cache coherence problem is the issue that arises when several copies of the same data are kept at various levels of memory. Until I enable the L1 cache, at which point I start getting interrupt 1023 being fired (‘spurious interrupt’ according to ARM docs). The practice of cache coherence makes sure that alterations in the contents of associated operands are quickly transmitted across the system. I am using FreeRTOS 8.2.1 on a TI AM4379 using the Cortex A9 port.Īll is well, I have 6 tasks running, interrupts are working…
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